circuit MACArraySetUp :
  module MACArraySetUp :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip dataIn : UInt<72>, flip wAddr : UInt<8>, flip valid : UInt<1>, flip clear : UInt<1>, flip lastvec : UInt<1>, flip switch : UInt<1>, nextRow : UInt, switchOut : UInt<1>[3], waddrOut : UInt, weOut : UInt<1>, clearOut : UInt<1>, doneOut : UInt<1>}

    reg waddrReg : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[macarraySetup.scala 27:31]
    waddrReg <= io.wAddr @[macarraySetup.scala 27:31]
    reg weReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[macarraySetup.scala 28:28]
    weReg <= io.valid @[macarraySetup.scala 28:28]
    reg clearReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[macarraySetup.scala 29:31]
    clearReg <= io.clear @[macarraySetup.scala 29:31]
    reg doneReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[macarraySetup.scala 30:30]
    doneReg <= io.lastvec @[macarraySetup.scala 30:30]
    wire _firstColumnReg_WIRE : UInt<8>[3] @[macarraySetup.scala 33:45]
    _firstColumnReg_WIRE[0] <= UInt<8>("h0") @[macarraySetup.scala 33:45]
    _firstColumnReg_WIRE[1] <= UInt<8>("h0") @[macarraySetup.scala 33:45]
    _firstColumnReg_WIRE[2] <= UInt<8>("h0") @[macarraySetup.scala 33:45]
    reg firstColumnReg : UInt<8>[3], clock with :
      reset => (reset, _firstColumnReg_WIRE) @[macarraySetup.scala 33:37]
    node _firstColumnReg_0_T = bits(io.dataIn, 7, 0) @[macarraySetup.scala 39:47]
    firstColumnReg[0] <= _firstColumnReg_0_T @[macarraySetup.scala 39:35]
    node _firstColumnReg_1_T = bits(io.dataIn, 15, 8) @[macarraySetup.scala 39:47]
    firstColumnReg[1] <= _firstColumnReg_1_T @[macarraySetup.scala 39:35]
    node _firstColumnReg_2_T = bits(io.dataIn, 23, 16) @[macarraySetup.scala 39:47]
    firstColumnReg[2] <= _firstColumnReg_2_T @[macarraySetup.scala 39:35]
    wire diagnonalWire : UInt<8>[3] @[macarraySetup.scala 43:33]
    wire _switchReg_WIRE : UInt<1>[3] @[macarraySetup.scala 52:40]
    _switchReg_WIRE[0] <= UInt<1>("h0") @[macarraySetup.scala 52:40]
    _switchReg_WIRE[1] <= UInt<1>("h0") @[macarraySetup.scala 52:40]
    _switchReg_WIRE[2] <= UInt<1>("h0") @[macarraySetup.scala 52:40]
    reg switchReg : UInt<1>[3], clock with :
      reset => (reset, _switchReg_WIRE) @[macarraySetup.scala 52:32]
    switchReg[0] <= io.switch @[macarraySetup.scala 55:38]
    switchReg[1] <= switchReg[0] @[macarraySetup.scala 57:38]
    switchReg[2] <= switchReg[1] @[macarraySetup.scala 57:38]
    reg io_waddrOut_r : UInt<8>, clock with :
      reset => (UInt<1>("h0"), io_waddrOut_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_waddrOut_r <= io.wAddr @[Reg.scala 17:22]
    reg io_waddrOut_r_1 : UInt<8>, clock with :
      reset => (UInt<1>("h0"), io_waddrOut_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_waddrOut_r_1 <= io_waddrOut_r @[Reg.scala 17:22]
    reg io_waddrOut_r_2 : UInt<8>, clock with :
      reset => (UInt<1>("h0"), io_waddrOut_r_2) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_waddrOut_r_2 <= io_waddrOut_r_1 @[Reg.scala 17:22]
    reg io_waddrOut_r_3 : UInt<8>, clock with :
      reset => (UInt<1>("h0"), io_waddrOut_r_3) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_waddrOut_r_3 <= io_waddrOut_r_2 @[Reg.scala 17:22]
    io.waddrOut <= io_waddrOut_r_3 @[macarraySetup.scala 62:21]
    reg io_weOut_r : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_weOut_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_weOut_r <= io.valid @[Reg.scala 17:22]
    reg io_weOut_r_1 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_weOut_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_weOut_r_1 <= io_weOut_r @[Reg.scala 17:22]
    reg io_weOut_r_2 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_weOut_r_2) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_weOut_r_2 <= io_weOut_r_1 @[Reg.scala 17:22]
    reg io_weOut_r_3 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_weOut_r_3) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_weOut_r_3 <= io_weOut_r_2 @[Reg.scala 17:22]
    io.weOut <= io_weOut_r_3 @[macarraySetup.scala 63:18]
    reg io_clearOut_r : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_clearOut_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_clearOut_r <= io.clear @[Reg.scala 17:22]
    reg io_clearOut_r_1 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_clearOut_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_clearOut_r_1 <= io_clearOut_r @[Reg.scala 17:22]
    reg io_clearOut_r_2 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_clearOut_r_2) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_clearOut_r_2 <= io_clearOut_r_1 @[Reg.scala 17:22]
    reg io_clearOut_r_3 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_clearOut_r_3) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_clearOut_r_3 <= io_clearOut_r_2 @[Reg.scala 17:22]
    io.clearOut <= io_clearOut_r_3 @[macarraySetup.scala 64:21]
    reg io_doneOut_r : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_doneOut_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_doneOut_r <= io.lastvec @[Reg.scala 17:22]
    reg io_doneOut_r_1 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_doneOut_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_doneOut_r_1 <= io_doneOut_r @[Reg.scala 17:22]
    reg io_doneOut_r_2 : UInt<1>, clock with :
      reset => (UInt<1>("h0"), io_doneOut_r_2) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      io_doneOut_r_2 <= io_doneOut_r_1 @[Reg.scala 17:22]
    io.doneOut <= io_doneOut_r_2 @[macarraySetup.scala 65:20]
    io.switchOut[0] <= switchReg[0] @[macarraySetup.scala 67:22]
    io.switchOut[1] <= switchReg[1] @[macarraySetup.scala 67:22]
    io.switchOut[2] <= switchReg[2] @[macarraySetup.scala 67:22]
    diagnonalWire[2] <= firstColumnReg[0] @[macarraySetup.scala 73:44]
    reg diagnonalWire_1_r : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_1_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_1_r <= firstColumnReg[1] @[Reg.scala 17:22]
    diagnonalWire[1] <= diagnonalWire_1_r @[macarraySetup.scala 73:44]
    reg diagnonalWire_0_r : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_0_r) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_0_r <= firstColumnReg[2] @[Reg.scala 17:22]
    reg diagnonalWire_0_r_1 : UInt<8>, clock with :
      reset => (UInt<1>("h0"), diagnonalWire_0_r_1) @[Reg.scala 16:16]
    when UInt<1>("h1") : @[Reg.scala 17:18]
      diagnonalWire_0_r_1 <= diagnonalWire_0_r @[Reg.scala 17:22]
    diagnonalWire[0] <= diagnonalWire_0_r_1 @[macarraySetup.scala 73:44]
    node io_nextRow_hi = cat(diagnonalWire[2], diagnonalWire[1]) @[macarraySetup.scala 75:37]
    node _io_nextRow_T = cat(io_nextRow_hi, diagnonalWire[0]) @[macarraySetup.scala 75:37]
    io.nextRow <= _io_nextRow_T @[macarraySetup.scala 75:20]

